ASML has delivered its groundbreaking High-NA EUV lithography scanner, the Twinscan EXE:5000, to Intel Oregon. Marking a significant technological leap, this first-of-its-kind scanner boasts a 0.55 NA lens, enabling 8nm resolution for advanced semiconductor manufacturing. Designed for process technologies beyond 3nm, it promises to enhance chip production efficiency and reduce costs. Intel's early adoption of this state-of-the-art equipment, valued between $300-$400 million, positions them at the forefront of the industry, potentially setting new standards in High-NA manufacturing. This development represents a major milestone in semiconductor technology, signaling a new era of innovation and capability in chip production.
Monday, January 8, 2024
Friday, December 29, 2023
TSMC Set to Revolutionize Chip Technology with Trillion-Transistor Packages by 2030
Monday, December 11, 2023
Intel Showcases Groundbreaking Transistor Innovations at IEDM 2023
At the 2023 IEEE International Electron Devices Meeting (IEDM), Intel introduced significant advancements in transistor technology that continue to drive Moore's Law forward. Intel's Components Research group demonstrated innovative 3D stacked CMOS transistors, enhanced with backside power and direct backside contacts. This breakthrough in transistor architecture allows for more efficient scaling and improved performance, marking a first in the industry.
3D Stacked CMOS Transistors
Intel displayed the ability to vertically stack complementary field effect transistors (CFET) with a scaled gate pitch down to 60 nanometers (nm). This technology, combined with backside power and direct backside contacts, underscores Intel's leadership in gate-all-around transistors and its capacity to innovate beyond RibbonFET.
Beyond Five Nodes in Four Years
Intel's PowerVia, set for manufacturing readiness in 2024, represents the first implementation of backside power delivery. At IEDM 2023, the company identified ways to extend and scale backside power delivery beyond PowerVia, utilizing backside contacts and other novel vertical interconnects for efficient device stacking.
Integration of Silicon and GaN Transistors
Intel successfully integrated silicon transistors with gallium nitride (GaN) transistors on the same 300 mm wafer. The "DrGaN" technology showcased at the event demonstrates Intel's advancements in high-performance integrated circuits for power delivery.
Advances in 2D Transistor Space
Intel presented high-mobility transition metal dichalcogenide (TMD) 2D channel materials, showcasing prototypes of high-mobility TMD transistors for both NMOS and PMOS. Additionally, Intel revealed the world’s first gate-all-around (GAA) 2D TMD PMOS transistor and the first 2D PMOS transistor fabricated on a 300 mm wafer.
These developments by Intel represent a significant stride in semiconductor research, promising to enhance the efficiency and capabilities of future computing technologies.
Friday, December 8, 2023
IBM and Samsung Revolutionize Semiconductor Industry with Groundbreaking VTFET Transistor Technology
Monday, October 23, 2023
TSMC To Report Breakthrough in NMOS Nanosheets Using Ultra-Thin MoS2 Channels at IEDM 2023
Monday, September 26, 2022
Bottom-up PEALD of SiO2 by growth inhibition for seamless gap-fill process
Bottom-up plasma-enhanced atomic layer deposition of SiO2 by utilizing growth inhibition using NH3 plasma pre-treatment for seamless gap-fill process
Saturday, May 8, 2021
Webinar - Decadal Plan for Semiconductors: New Compute Trajectories for Energy Efficiency
Friday, April 30, 2021
The US Patent Office has approved AlixLabs’ patent application for nanofabrication by ALE Pitch Splitting (APS)
Saturday, March 6, 2021
Thermal ALE of germanium rich SiGe by CU Boulder and ASM Microchemistry
Wednesday, February 3, 2021
LIVE Stream - Advanced Process Technologies to Enable Future Devices and Scaling (invited), Rob Clark Tokyo Electron
Thursday, January 21, 2021
Master Thesis in Nanotechnology with Alixlabs in Sweden on Atomic Level Fragmentation
Thursday, December 17, 2020
Imec introduces 2D materials in the logic device scaling roadmap
More details can be found in 4 papers presented at the 2020 IEDM conference:
[1] ‘Introducing 2D-FETs in device scaling roadmap using DTCO’, Z. Ahmed et al.
[2] ‘Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab’, I. Asselberghs et al.
[3] ‘Dual gate synthetic WS2 MOSFETs with 120µS/µm Gm 2.7µF/cm2 capacitance and ambipolar channel’, D. Lin et al.
[4] ‘Sources of variability in scaled MoS2 FETs’, Q. Smets et al. (IEDM highlight paper)
Thursday, November 19, 2020
Intel to present 3D stacked Nanoribbon Transistors for Continued Moore’s Law Scaling at IEDM 2020
Paper Information (IEDM 2020) : LINK
·
(1) shows
the evolution of transistor architectures from planar, to FinFETs, to
nanoribbons and to a 3D CMOS architecture.
·
(2) (a)
shows a 3D schematic diagram of stacked CMOS Si nanoribbon transistors with
NMOS on PMOS, (b) describes the process flow; (c) is a TEM image of a stacked
multiple-nanoribbon CMOS inverter with a 40-nm gate length and inner (Vss)
and outer (Vcc) contacts, a common gate input (VIN) and
an inverter output node (VOUT); while (d) is a TEM image of two Si
NMOS nanoribbons atop 3 Si PMOS nanoribbons.
·
(3) (a)
is a process flow of the vertically stacked dual S/D EPI process, while (b)
shows P-EPI selectively grown on the bottom three nanoribbons, (c) shows N-EPI
selectively grown on the top two nanoribbons, and (d) features TEM and EDS
images showing selective N-EPI and P-EPI growth on the stacked nanoribbon
transistors.
·
(4)
(a) is a process flow of the vertically stacked dual metal gate process; (b) is
a TEM image and (c, d) are EDS images of the dual metal gate with N-WFM (WFM =
work function metal) on the top two nanoribbons and P-WFM on the bottom three
nanoribbons.
Thursday, April 2, 2020
TSMC hit by 3nm delay fears over Covid-19 Lock-downs
Below a comparison of the Covid-19 daily new confirmed deaths, which is the only comparable parameter to use due to different testing capabilities and frequencies, in time and nation to nation. As can be seen the situation in Asian is under control after the gotten hit by the first wave of the Coronavirus. The European situation is stabilizing: Italy, Netherlands, Germany France, others look similar and are flattening the curve. In The USA situation is escalating. Many nations in Europe are forecasting a lift of Lockdown in May but are very careful, as an example Germany will decide in 19 April how to proceed according to Chancellor Dr. Angela Merkel.
BALD Engineering AB continues to monitor the Covid-19 situation due to lockdowns that affect the the semiconductor industry – Stay Safe!
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By Abhishekkumar Thakur, Jonas Sundqvist
Friday, January 24, 2020
Russian researchers obtain atomically thin molybdenum disulfide (2D) films on large-area substrates by ALD
An atomic layer deposition reactor from Picosun used for obtaining ultrathin molybdenum oxide films, which were subsequently sulfurized to 2D molybdenum disulfide. Image courtesy of the Atomic Layer Deposition Lab, MIPT
Two-dimensional materials are attracting considerable interest due to their unique properties stemming from their structure and quantum mechanical restrictions. The family of 2D materials includes metals, semimetals, semiconductors, and insulators. Graphene, which is perhaps the most famous 2D material, is a monolayer of carbon atoms. It has the highest charge-carrier mobility recorded to date. However, graphene has no band gap under standard conditions, and that limits its applications.
Saturday, December 14, 2019
IEDM 2019 News - Intel roadmap to 1.4 nm by 2029
Wednesday, December 11, 2019
Imec shows excellent performance in ultra-scaled FETs with 2D-material channel
MoS2 is a 2D material, meaning that it can be grown in stable form with nearly atomic thickness and atomic precision. Imec synthesized the material down to monolayer (0.6nm thickness) and fabricated devices with scaled contact and channel length, as small as 13nm and 30nm respectively. These very scaled dimensions, combined with scaled gate oxide thickness and high K dielectric, have enabled the demonstration of some of the best device performances so far. Most importantly, these transistors enable a comprehensive study of fundamental device properties and calibration of TCAD models. The calibrated TCAD model is used to propose a realistic path for performance improvement. The results presented here confirm the potential of 2D-materials for extreme transistor scaling – benefiting both high-performance logic and memory applications.
Saturday, November 23, 2019
Imec updates semiconductor miniaturization roadmap to 1nm-ITF Japan 2019
This is what we are to expect coming next for Logic scaling: Nanosheet transistors (Gate All Around transistors), Buried Power Rails, Ruthenium incorporation, Forksheet transistor architecture, CFET (complementary FET by 3D stacking of nanosheet PFET and NFET), deployment of 2D materials, spintronics, and quantum computing as the way to continued chip scaling for keeping a modified Moore's Law alive.
Tuesday, October 15, 2019
Lund University Holding invests in newly started AlixLabs
LU Holding invests in newly started AlixLabs, which have developed a method to manufacture electronic circuits for the semiconductor industry in a very cost-effective way.
[Published on September 27, 2019: Original in Swedish: LINK]
Researchers from NanoLund have developed and patented the method and all three, Jonas Sundqvist, Dmitry Suyatin, and Sabbir Kahn, are part of the newly started company (AlixLabs AB), and Co-founder Stefan Svedberg joins as CEO. Svedberg was previously Director of Corporate Development at Ericsson.
Displaying the Edge Effect: This is a new method of nanostructure fabrication using the atomic layer etching process, which is inherently a damage-free etch process. The recently discovered etching process selectivity to inclined surfaces, can be used as a mask and in this way walls of tapered structures. The inclined surfaces can be readily fabricated by e.g. dry etching or epitaxial growth, and will provide masking during the atomic layer etching process. This process therefore provides access to fabrication of extremely small structures in a very precise and efficient way.
Electronic circuits are needed in all types of hardware, but the cost of producing them has increased as the electronics become smaller. With the AlixLab method, which is based on a recently identified physical phenomenon, the manufacturing process of the electronic circuits becomes both faster and significantly cheaper.
Alixlabs plans to implement an expanded proof of concept in 2020 as the basis for continued customer discussions.
Tuesday, September 24, 2019
Moore's Law graphed vs real CPUs & GPUs 1965 - 2019
(Youtube: https://www.youtube.com/watch?v=7uvUiq_jTLM) Moore's Law has been ridiculously accurate for more than 50 years - how long will it hold up? See in this visualization how the actual transistors in CPUs and GPUs compare to the linear progression of Moore's Law. From the early days of microprocessors, to Intel dominance and the rise of GPUs.