Showing posts with label ASML. Show all posts
Showing posts with label ASML. Show all posts

Saturday, November 28, 2020

Applied Materials will regain its No. 1 ranking in the semiconductor equipment market in 2020 from ASML

According to recent published data by The Information Network (Seeking Alpha LINK), Applied Materials will regain its top ranking in the semiconductor equipment market in 2020 from ASML. Fab equipment spend in 2020 was enhanced from pull-ins of sales into China and Taiwan, with 3Q QoQ increases of 22.5% and 36.2%, respectively.

As is well known ASML and Applied Materials does not compete in their  business segments, Lithography (ASML) resp. Deposition & Etch (Applied Materials). Applied Materials has a number 1 spot in PVD, CVD, Epi, CMP and Implant/Doping. However, business segments where Applied Materials so far has not been successful to reach a top 3 position in the past years include:
  • Atomic Layer Deposition
  • MOCVD
  • Furnace 
  • Dielectric Etch  
  • Spray Processing
  • Dielectric Etch (including ALE)
  • Wet Stations
As is known, Applied Materials have several times made very serious attempts to enter the ALD segment, but failed several times to compete with ASMI, Tokyo Electron and the South Korean OEMs (Jusung Engineering, Wonik IPS and Eugene Technology. In 2019 Applied Materials announced that it will acquire Japanese Kokusai (LINK) but the final agreement is yet not settled. If successful Applied will have an opportunity to kill 2 birds with one stone:

1. Move in to top 3 spot in ALD
2. Take number 2 spot in Furnace business


Table based on information and own assumptions in the article (Seeking Alpha LINK)

Thursday, April 2, 2020

TSMC hit by 3nm delay fears over Covid-19 Lock-downs

TSMC is on schedule with its 5 nm process plan, but its 3 nm trial production may get delayed: The world's largest contract chipmaker is planning to launch mass production of its 3 nm process sometime in 2022, and media reported Monday that installation of production equipment in its 3 nm wafer fab in Tainan will be delayed to October from June this year, which will delay its trial production set for 2021. The COVID-19 escalation has hit Europe, and [Netherlands-based] ASML Holding, which is TSMC's major production equipment supplier, has been affected by a lockdown. It is understandable that the progress of TSMC's new technology has been affected.

Below a comparison of the Covid-19 daily new confirmed deaths, which is the only comparable parameter to use due to different testing capabilities and frequencies, in time and nation to nation. As can be seen the situation in Asian is under control after the gotten hit by the first wave of the Coronavirus. The European situation is stabilizing: Italy, Netherlands, Germany France, others look similar and are flattening the curve. In The USA situation is escalating. Many nations in Europe are forecasting a lift of Lockdown in May but are very careful, as an example Germany will decide in 19 April how to proceed according to Chancellor Dr. Angela Merkel.

BALD Engineering AB continues to monitor the Covid-19 situation due to lockdowns that affect the  the semiconductor industry – Stay Safe!

Google Finance (2020-04-02, 10:39 CET)

Sources:

Taiwan shares edge lower, TSMC hit by 3nm delay fears

Our World of data: https://ourworldindata.org/coronavirus

-----------
By Abhishekkumar Thakur, Jonas Sundqvist

Saturday, January 4, 2020

EUV - The Extreme Physics Pushing Moore’s Law to the Next Level

Have a look into the EUV tool with ASML engineers describing the whole technology and their devotion to make it really happening when many geniuses in the industry refused to believe in the possibility.

  
The Extreme Physics Pushing Moore’s Law to the Next Level (Youtube.com)
----------
By Abhishekkumar Thakur

Saturday, December 14, 2019

IEDM 2019 News - Intel roadmap to 1.4 nm by 2029

Limitless - Intel disclosed its extended roadmap to 1.4 nm process node by 2029 including back porting: One of the interesting disclosures at the IEEE International Electron Devices Meeting (IEDM) was that Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7 nm EUV in 2021, then 5 nm in 2023, 3 nm in 2025, 2 nm in 2027, and 1.4 nm in 2029. 
 
In between each process node, as Intel has stated before, there will be iterative + and ++ versions of each in order to extract performance from each process node. The only exception to this is 10nm, which is already on 10+, so we will see 10++ and 10+++ in 2020 and 2021 respectively. The interesting element is the mention of back porting. This is the ability for a chip to be designed with one process node in mind, but perhaps due to delays, can be remade on an older ‘++’ version of a process node in the same timeframe.

 
Intel's slide with ASML's animations overlayed, as shown in the slide deck distributed by ASML. Note by Anandtech: "After some emailing back and forth, we can confirm that the slide that Intel's partner ASML presented at the IEDM conference is actually an altered version of what Intel presented for the September 2019 source. ASML added animations to the slide such that the bottom row of dates correspond to specific nodes, however at the time we didn't spot these animations (neither did it seem did the rest of the press). It should be noted that the correlation that ASML made to exact node names isn't so much a stretch of the imagination to piece together, however it has been requested that we also add the original Intel slide to provide context to what Intel is saying compared to what was presented by ASML. Some of the wording in the article has changed to reflect this. Our analysis is still relevant." Please see the full article in Anandtech for all the details: LINK
 
----------
By Abhishekkumar Thakur

Saturday, March 16, 2019

VLSIresearch released its list of the top Semiconductor Equipment Suppliers for 2018 shown big wins for Japanese OEMs

VLSI Research report well above average growth for ASML (NL), Tokyo Electron (JPN), Advantest (JPN), Kokusai (JPN), Daifuku (JPN) and Canon (JPN) so a big win for Japan and the Netherlands last year. All Japanese companies outperform the market growth 2018!

Dan Hutchenson: "VLSIresearch released its list of the top Semiconductor Equipment Suppliers for 2018. Notable shifts were TEL passing Lam to take the top spot. Advantest past Screen for 7th with the highest growth of any chip equipment manufacturer. While ASM Pacific passed SEMES. For details, see: https://lnkd.in/gDxccnX

Most growth is seen in Litho as for each Immersion or EUV tool that is installed a bunch of Tokyo Electron tools come as well like e.g. the TEL Track platform.

With respect to ALD, judging by ASMI, TEL and Kokusai it seems that ALD was able to capture all of the growth in 2018 and maybe a bit more. In April the Japanese companies start their 2018 annual reporting so then we will know more for now we have the ASMI report to study (LINK).



Tuesday, October 23, 2018

Imec and ASML Enter Next Stage of EUV Lithography Collaboration

Intensified collaboration will advance high-volume production with current EUV lithography and develop future EUV systems

LEUVEN (Belgium) & VELDHOVEN (The Netherlands), OCTOBER 22, 2018 (LINK) —Today, world-leading research and innovation hub in nanoelectronics and digital technologies imec, and ASML Holding N.V. (ASML), the technology and market leader in lithographic equipment, announce the next step in their extensive collaboration. Together, they will accelerate the adoption of EUV lithography for high-volume production, including the current latest available equipment for EUV (0.33 Numerical Aperture, NA). Moreover, they will explore the potential of the next-generation high-NA EUV lithography to enable printing of even smaller nanoscale devices advancing semiconductor scaling towards the post 3 nanometer Logic node. To this end, they will establish a joint high-NA EUV research lab.

Imec and ASML have been conducting joint research for almost thirty years. In 2014, they created a joint research center, the Advanced Patterning Center, to optimize lithography technology for advanced CMOS integration and to prepare the ecosystem to support advance patterning requirements. Now, they bring this cooperation to the next stage with the installation of ASML’s most advanced and high-volume production dedicated EUV scanner (NXE:3400B) in imec’s cleanroom. Utilizing imec’s infrastructure and advanced technology platforms, imec and ASML researchers and partner companies can pro-actively analyze and solve technical challenges such as defects, reliability and yield, and as such accelerate the EUV technology’s industrialization.