Thursday, February 6, 2014

PVD Free processes used for future emerging memory technologies

This week at the Fraunhofer IPMS-CNT Industry Day, Malgorzata Jurczak, Director Emerging Memory Devices - IMEC, stated that "PVD-free processes (ALD/CVD) are needed for Emerging Memory" To visualize this in the case of 3D NAND there is a recent blog post (SemiMD.com) on the topic - and yes obviously PVD and also not CVD can´t be an option for these highly scaled 3D architectures. Below is a brief snapshot [complete story here]

"The current iteration of NAND flash technology, 2D – or planar – NAND, is reaching its limits. In August 2013, South Korean consumer electronics brand Samsung announced the launch of its 3D NAND storage technology, in the form of a 24-layer, 128 GB chip. In 2014, memory chipmakers Micron and also SK Hynix will follow suit, heralding the arrival of a much-anticipated and debated technology during various industry conferences in recent years. Other companies, including Sandisk, are all working on 3D NAND flash technology." as reported by
Sara Ver-Bruggen, contributing editor at Semiconductor Manufacturing and Design.

“Everything in 3D is a significant challenge. With vertical scaling the challenges include etching high aspect ratio holes, with the aspect ratio doubling with each doubling of layers. These holes must have absolutely parallel walls or scaling and device operation may be compromised. If the layers are thinned then the atomic-layer deposition (ALD) of the layers must be able to apply a constant thickness layer across the entire wafer, which is also true of the layers that are deposited on the walls of the hole,” according to Handy. [Jim Handy from Objective Analysis, who is writing aboute NAND and 3D NAND in the Memory Guy Blog]

 
3D NAND manufacturing considerations and challenges - Staircase etching requires very precise contact landing and the ALD process has to be applied with a constant thickness in 3D across the whole 300mm wafer. Obviously PVD or CVD is not an option at all. These staircase contacts could have an 60:1 aspect ratio.
Chuck Dennison, Senior Director Process Integration, from Micron, explained for 3DNAND “There is a lot planarization, you are etching very high aspect ratio contacts where you need to be very controlled, in terms of how you define your control and CD uniformity. Then there are a lot of additional modules requiring ALD deposition. So we think that there is a lot of opportunity to utilize our DRAM expertise.”